Many up-to-date data processing systems require data to be buffered while transferring the data between master and slave devices, such as central processing units (CPU) and memories. Data buffering can be performed by a data pipeline where data is stored in a first register with a first clock signal. From the first register the data is transferred to a second register by a second clock signal. The relationship between the two clock signals, in particular the clock phases, underlie certain restrictions. The second clock phase must be in a certain time frame with regard to the phase of the first clock signal. For a fast data transfer more restrictions are to be taken into account. Many applications require that the timing of the first register (pre-register timing) is decoupled from the timing of the second register (post-register timing). The pre-register timing can be in a noisy environment while the post-register side requires a noise-free signal. A buffer circuit for DDR3 applications is a typical example of such an application. Typically, a two flip-flop or a flip-flop and latch pipeline is used in conventional data pipeline architectures. The respective circuits are shown in FIGS. 1(a) and (b). Usually, the first clock CLK1 and the second clock CLK2 are in phase and the input data of the first flip-flop FF1 appears only after a specific edge of the second clock signal CLK2 at the output of the second flip-flop FF2. The propagation delay time of the signals is 1 clock period plus the propagation delay time (TPD) from CLK2 to the output Q2 of the second flip-flop. In order to speed up the system, the phase of the second clock CLK2 might be shifted closer to the phase of the first clock CLK1. However, the limit is the propagation delay time of the first flip-flop FF1 and set-up time of the second flip-flop FF2. Carefully designed in today's high-speed technologies, the delay can range from 300 up to 600 ps. This corresponds to approximately four gate delays in the respective technology. The overall propagation delay can be reduced by 200 ps, if the second flip-flop is replaced by a latch as shown in FIG. 1 (b). A low to high transition of the second clock CLK2 switches the latch into the transparent mode. The latch is in transparent mode before the data arrives at Q1, the data will be triggered by the first clock signal CLK1. If the latch is turned into transparent mode after the data arrives at Q1, the data transfer from the flip-flop to the latch is basically triggered by the second clock signal CLK2. In the first case, the flip-flop and latch timing is not decoupled but delivers the fastest data transfer rate. In order to decouple the pre-and post-register timing, the latch has to be switched in non-transparent mode before a new data arrives at Q1. This can be achieved by shifting the phase of the second clock signal CLK2 to less than 180 degrees of the clock period dependent on the duty cycle and the whole time of the latch. However, this limits the tuning range of the second clock phase.